Distributive power supplies have found wide application, as, for example, in telecommunications and data processing systems. This class of power supply provides an advantage over bulk power systems by reducing parasitic reactances between the power supply and components connected to the supply. See Application Note #6, TachoMOD Demonstration Board, Vicor Corporation, Andover, Mass., July 1991; and Prager, Jay, "Beyond Distributed Power", Vicor Corporation, Andover, Mass. Dec. 21, 1990. In general these power supplies provide a source of power to a common bus system (known as a "backplane" system) so that high speed digital signals can be transmitted among various components all connected to the backplane system so as to form a larger electronic system.
Backplane systems or motherboards are widely used today to overcome numerous problems arising out of the huge number of wires often required to effect connections between cardedge connector pins. The term "backplane" is understood to refer to a board or sheet of electrically insulating material, such as a glass-epoxy composite, provided with a plurality of electrically conductive channels or busses that run parallel to one another across one or more surfaces of the backplane between one or more male or female electrical connectors coupled to the busses. The backplane can be thus considered as the neural network of an electronic system in that it provides the interconnection of components of the system, usually in the form of various "function boards" or "daughter boards", each comprising a multiplicity of printed circuit boards.
In a bussed backplane, the majority of the interconnections are formed by contacts on connectors provided on each function or daughter board. The contacts are typically oriented perpendicular to the direction of the bussed connections at locations on the backplane called slots. Such backplanes may also have point to point connections which go from a contact on one connector to a single point on another connector. There may also be connections that interconnect more than two points but which are not fully bussed or have no bussed section.
As the demands of increased operating speeds on backplane systems have increased, so have the performance demands on distributive, power sources. For example, BTL systems have recently been developed, such as the Futurebus+ system manufactured and sold by the present assignee, Hybricon Corporation of Ayer, Mass., which allow much faster propagation time of digital signals through the backplane bus, than previously achieved by the earlier Versa-module Europe (VME) system.
The former VME system uses TTL logic for each transceiver connected to the bus. As such there is a larger capacitive load which slows down signal propagation in a VME system. Furthermore, as the result of TTL logic, a greater swing of voltage is required between the high and low states of the digital signals on the bus. In order to reach the TTL logic threshold, a change in the signal voltage on the bus must travel past all of the slots of the bus in the forward direction; then reflect back to the source. Consequently, these VME systems are ref erred to as second incident wave systems.
BTL systems, on the other hand, employ a family of transceivers with much lower parasitic output capacitance so that the signal propagation delay is reduced and with smaller voltage swing so that "incident" wave switching systems can be provided. This family of transceivers, specified in the IEEE 1194.1 documentation, has become the basis for a high performance computing system such as the Futurebus+ system. Known as Backplane Transceiver Logic, or BTL, this transceiver family has also become popular for computer and telecommunications applications. A BTL transceiver is an open collector device with a series Schottky Barrier diode for isolating the collector capacitance from the bus when the transceiver is off (in the high state).
For effective transmission of high speed digital signals in backplanes using the incident wave mode of operation, each bussed transmission line must be terminated at each end with a resistive termination R.sub.T (see FIG. 1) which matches the characteristic impedance of the line provided by the bus. Furthermore, these termination resistors need to be connected to a power source so that the resistors act as pullups when a particular line changes from a low state to a high state, and thus provide the means of establishing the logic high level voltage on the bus as the default state. As is well known, the bus voltage must be then switched from high to low, by transceivers located on the function and daughter boards that plug into the backplane at various slot positions (shown for example at SL.sub.1 through SL.sub.7 in FIG. 1) when a low state is initiated. The termination resistors R.sub.T, located at each end of the bus, are connected to a power source V.sub.T, so as to provide the proper voltage level, typically set at 2.1.sup.V DC, which establishes a logic high level equal to the power source voltage. This is also shown in FIG. 1. The nominal logic low voltage is approximately 1.sup.V DC and the nominal, mean threshold voltage is approximately 1.54.sup.V DC. FIG. 1 shows the various voltage limits. Transition times between the high and low states vary typically between 2ns. and 5ns., but can be faster.
As a result a signal voltage front (caused by a change in state) travels down a backplane past each slot and does not reflect back appreciably (and for this reason is referred to as an "incident wave switching" system). The signal can be accepted by any board. Theoretically, a transceiver driver can put another change of signal on the backplane before the signal front of the previous one has reached the end of the backplane.
The requirement, problems and solutions described herein, are described in connection with the transmission of high speed digital signals on backplane systems and, preferably in bussed backplane interconnection systems that will support incident wave switching operation of the system. Incident switching, by its nature, places very serious demands on the speed and signal integrity capability of the system. However, the application, problems and solutions described herein, are appropriate for a wider range of backplane system applications.
In order to understand the problems of the prior art reference is made to FIG. 2. FIG. 2 shows a simplified representation of one end of a typical backplane signal transmission system meeting the Futurebus+ specification, wherein two of the slots n-1 and n are shown connected to 64 data bit lines of the signal bus 10 connected to the pullup, terminating resistors R.sub.t1 -R.sub.t64. Each successive pair of data bit lines R.sub.t1 and R.sub.t2, R.sub.t3 and R.sub.t4, . . . R.sub.t63 and R.sub.t64 have their terminating resistors connected as a pair to the ground plane of the backplane through a single bypass capacitor C.sub.3.
Capacitor C.sub.3 is preferably a ceramic (i.e., tantalum and aluminum electrolytic) capacitor connected in parallel to one or two stages of larger or main capacitors C.sub.2 and C.sub.1, as well as the power supply 12, all of which have one plate or terminal connected to the ground plane. The larger capacitors are provided in order to supply charging current to each successively smaller capacitor. Capacitors C.sub.3,1 ; C.sub.3,2 . . . C.sub.3,n are the primary source of stored energy needed to supply current to the termination resistors R.sub.T, initially, at the moment a transceiver switches T on, and likewise, absorb the excess current when the transceiver switches off. They will discharge (or charge) at an initial rate determined by the maximum current demand which can be a number of amperes when the maximum possible number of lines switch simultaneously. When one of the data bit lines changes state from a high state to a low state, for example, charge is pulled from the corresponding capacitor C.sub.3, resulting in a decrease in voltage across this capacitor. For stability of the high voltage state of reference voltage provided across the terminating resistor on the line, the capacitor must be charged as quickly as possible. By making capacitor C.sub.2 &gt;&gt;C.sub.3, and C.sub.1 &gt;&gt;C.sub.2, the discharging capacitor C.sub.3 will be quickly charged by capacitor C.sub.2, which in turn will be quickly recharged by capacitor C.sub.1, with the latter being recharged by the 2.1.sup.V DC power supply.
The inductances L.sub.4,1a, L.sub.4,2a . . . L.sub.4,32a, L.sub.4,1b, L.sub.4,2b . . . L.sub.4,32b, L.sub.3a, L.sub.3b, L.sub.2a, L.sub.2b, L.sub.1a L.sub.1b, all represent the unavoidable series interconnection parasitic inductance of each charge and discharge path of each capacitor. The circuit also shows the possible sense points for the two power supply sense connections.
From this circuit schematic, it can be readily seen that when one or more lines are switched, significant crosstalk voltage can be injected into other lines. For example, when the line for bit 1 is switched by any transceiver connected to it, the dv/dt of the rising or falling edge of the signal current will generate a voltage across L.sub.4,1a and L.sub.4,1b which will appear as a pulse at the junction of R.sub.t1 and R.sub.t2 and thus on bus line for data bit 2, attenuated as a function of R.sub.t2 and impedance output Z.sub.o of line 2.
Since capacitors C.sub.3,1 ; C.sub.3,2 . . . C.sub.3,n are the primary source of stored energy needed to supply current to the termination resistors, and they will discharge (or charge) at an initial rate determined by the maximum current demand, any voltage change, across these capacitors, due to current drawn by driven lines will appear as crosstalk across undriven lines as well as each driven line seeing the crosstalk from all the other driven lines.
For many general, digital circuit applications, a sufficiently stable voltage source for switched current applications (which typically use feedback amplifiers to provide the necessary currents to maintain a stable voltage) is provided using a conventionally current regulated power supply with a set of low ESR capacitors. For more precise applications, however, this system does not work well.
Use of such low ESR capacitors with the parasitic inductances create resonant frequencies in the feedback of an amplifier of a current regulator causing undesirable ringing of the circuit at the resonant frequencies. The series inductances need to be reduced and a different type of supply, with faster and different response characteristics, is therefore needed to solve the problem.
Until the present invention, it has been difficult to develop a faster response time of a current regulator of a power supply for a backplane system. We believe that the reason a fast responding current regulator has not been developed is because of the high series parasitic inductances. The errors due to the series parasitic inductances, which are partly in the capacitors and partly in the printed circuit interconnections, and the errors due to the equivalent series resistances, which are inherent in ceramic capacitors, are totally unacceptable for the application.
For more precise applications of the power supply of a backplane system, remaining problems include (a) transient response of the current regulator, (b) output impedance and (c) the parasitic inductance between the power supply and the high speed BTL logic devices. Prager, supra, suggests that part of the solution to the problem arising out of parasitics and a DC-DC converter module is to use "external capacitance at the load sites, to overcome control response and transient voltage problems at the point of load, inherent to traditional converters. By having essentially all of the output capacitance outside the converter module, at the points of load, parasitic inductances between the converter and the load are lumped into the output inductance of the converter, thus eliminating constraints on the slew rate of the voltage feeding the parasitics." Thus, the system described by Prager is a "voltage compliant system".
However, applying the teachings of Prager as well as the prior art precision voltage references (as described hereinafter) used for successive approximation analog-to-digital converters in order to provide a fast recovery after the application of a current step function to a backplane system is not satisfactory because of inherent parasitic impedances created in the current paths between the sense points, as well as the load capacitor itself.